1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device having a layered gate structure with a shallow trench isolation (STI) element isolation insulating film and a method of manufacturing the same.
2. Description of the Related Art
Along with the recent size reduction of semiconductor memory devices, element isolation by self-aligned shallow trench isolation (STI) is becoming popular. In element isolation using STI, the width of STI in the memory cell region is minimized, and the STI is made shallow to minimize the aspect ratio in gap filling so as to ensure the STI gap filling capability. In the peripheral circuit portion to control the memory cell, however, the dielectric isolation between elements is more necessary than memory cells. To ensure the dielectric isolation, the STI in the peripheral circuit region is deeper than the STI in the memory cell region (see e.g., Jpn. Pat. Appln. KOKAI Publication No. 2002-368077).
However, if the dielectric isolation in the peripheral circuit region is to be further improved, the STI cannot be deepened because of the restrictions on the STI gap filling capability. Instead, in the peripheral circuit region, the STI is made higher than in the memory cell region. In this case, however, the following problems are posed.
The STI is high in the peripheral circuit region and low in the memory cell region. For this reason, the height from the surface of the silicon substrate to the mask material of the gate wiring is large in the peripheral circuit region and small in the memory cell region. If the gate wiring is to be buried by an insulating film, and planarization by chemical mechanical polishing (CMP) is to be executed, a barrier layer deposited on the mask material of the gate wiring is used as the stopper of CMP. However, since the height to the mask material changes between the memory cell region and the peripheral circuit region, the barrier layer in the peripheral circuit region where the mask material is high is excessively polished by CMP. For this reason, the barrier layer on the peripheral circuit region side becomes thin at the boundary between the memory cell region and the peripheral circuit region, or the barrier layer is completely lost. In addition, the difference in height to the barrier layer between the peripheral circuit region and the memory cell region (the step difference between the memory cell region and the peripheral circuit region) influences metal interconnection formation to be performed later. Hence, a resolution failure occurs in lithography at the step portion of the boundary region.